Buffer insertion with accurate gate and interconnect delay computation

TLDR

Buffer insertion is critical in deep submicron design, yet existing algorithms rely on simplified delay models that can yield suboptimal solutions. We aim to improve buffer insertion by integrating accurate wire and gate delay models into Van Ginneken’s algorithm. This is achieved by propagating moments and driving‑point admittances up the routing tree. Our approach was validated on an industry design, demonstrating its effectiveness.

Abstract

Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these methods use simplified interconnect and gate delay models. These models may lead to inferior solutions since the optimized objective is only an approximation for the actual delay. We propose to integrate accurate wire and gate delay models into Van Ginneken's buffer insertion algorithm (1990) via the propagation of moments and driving point admittances up the routing tree. We have verified the effectiveness of our approach on an industry design.