Compiler optimization on instruction scheduling for low power

Abstract

We investigate compiler transformation techniques for the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case we prove that the problem is NP-hard and propose a heuristic algorithm. Experimental results show average 13% improvements with the 4-way issue architecture and average 20% improvement with the 8-way issue architecture for power consumption of the instruction bus as compared with conventional list scheduling for an extensive set of benchmarks.