Publication | Closed Access
Improving routing efficiency for network-on-chip through contention-aware input selection
33
Citations
14
References
2006
Year
EngineeringEdge ComputingRouting TechniquesNetwork Traffic ControlRouter ArchitectureComputer EngineeringComputer ArchitectureSystems EngineeringRouting EfficiencyNetwork On ChipRouter DesignComputer ScienceOutput SelectionInterconnection Network ArchitectureParallel ComputingContention-aware Input Selection
The performance of network-on-chip (NoC) largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for NoC has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection (CAIS) technique for NoC that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, CAIS decides which input channel obtains the access depending on the contention level of the upstream switches, which in turn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, CAIS achieves significant better performance than the traditional first-come-first-served (FCFS) input selection, with low hardware overhead (<3%).
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