CMOS gate array implementation of the SPARC architecture

Abstract

A description is given of the MB86900 processor, the first implementation of Sun Microsystems' Scalable Processor Architecture (SPARC). MB86900, referred to here as the integer unit (IU), is a high-performance microprocessor designed with high-speed CMOS gate-array technology. In a typical system, the MB86900 IU works with a companion floating-point controller chip (the MB86910), two commercial floating-point arithmetic processors, and a cache. The MB86900 has a reduced-instruction-set-computer (RISC) architecture that defines a simple, yet efficient set of instructions. Most of these instructions execute in a single cycle, resulting in a very low average number of cycles per instruction. The simplified format of the instructions allows the source operands to be read immediately from the register file without any delay caused by the decoding of instructions, significantly decreasing the cycle time. The processor has a large on-chip register file that reduces the overhead of load and store operations considerably, allowing a peak execution rate of approximately 1 cycle per instruction when all operands are kept inside the processor's register file.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>