Publication | Closed Access
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
238
Citations
51
References
2016
Year
Unknown Venue
EngineeringMachine LearningHardware AlgorithmComputer ArchitectureHardware SystemsHardware SecurityComputing SystemsEmbedded Machine LearningPerformance ImprovementComputer EngineeringComputer ScienceDeep LearningNeural Architecture SearchDeep Neural NetworksHardware AccelerationEnabling Low-powerAccelerator BaselineDomain-specific AcceleratorSpecialized Hardware
The continued success of Deep Neural Networks in classification tasks has spurred a trend of accelerating their execution with specialized hardware, yet most designs stop at an initial implementation. This paper presents Minerva, a highly automated co‑design approach across algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Minerva employs fine‑grained heterogeneous data‑type optimization, aggressive inline predication and pruning of small activity values, and active hardware fault detection with domain‑aware error mitigation to reduce power. Compared to a fixed‑point baseline, these optimizations achieve an average 8.1× power reduction across five datasets without compromising accuracy, enabling ultra‑low‑power DNN accelerators in the tens of milliwatts range suitable for IoT and mobile devices.
The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous data type optimization reduces power by 1.5×, aggressive, in-line predication and pruning of small activity values further reduces power by 2.0×, and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7× through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1× power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.
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