ACM SIGPLAN Notices · 2009 · 36 citations · 8 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureFormal MethodsParallel ComputingAssertion-based VerificationControl-flow AnalysisData-flow AnalysisModel CheckingParallel Programming ModelsVerificationAssertion CheckingFormal Safety VerificationFormal VerificationOpenmpParallelizationPartial-order ReductionSafety PropertiesVerification Methodology
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our approach, we directly model-check the MPI/C source code, executing its interleavings with the help of a verification scheduler. Unfortunately, the total feasible number of interleavings is exponential, and impractical to examine even for our modest goals. Our earlier publications formalized and implemented a partial order reduction approach that avoided exploring equivalent interleavings, and presented a verification tool called ISP. This paper presents algorithmic and engineering innovations to ISP, including the use of OpenMP parallelization, that now enables it to handle practical MPI programs, including:(i)~ParMETIS - a widely used hypergraph partitioner, and (ii)~MADRE - a Memory Aware Data Re-distribution Engine, both developed outside our group. Over these benchmarks, ISP has automatically verified up to 14K lines of MPI/C code, producing error traces of deadlocks and assertion violations within seconds.
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Dynamic partial-order reduction for model checking software
Cormac Flanagan, Patrice Godefroid · 2005 · 641 citations · Full text
Madanlal Musuvathi, Shaz Qadeer · 2008 · 91 citations