In-memory processing paradigm for bitwise logic operations in STT-MRAM

Abstract

In current big data era, the limited data bandwidth (memory wall) between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In this work, we propose a cost-efficient IMP solution in STT-MRAM without adding any processing units on the memory chip. The key idea behind the proposed IMP solution is to exploit the peripheral circuitry already existing inside memory (or with minimal changes) to perform bitwise logic operations.