Publication | Closed Access
The scalable processor architecture (SPARC)
37
Citations
9
References
1988
Year
Unknown Venue
Scalable Processor ArchitectureEngineeringCompiler TechnologySparc ArchitectureMany-core ArchitectureComputer EngineeringComputer ArchitectureBerkeley RiscWord (Computer Architecture)Integer ComputationComputer ScienceProcessor ArchitectureParallel ComputingManycore ProcessorHardware SystemsSystem SoftwareInstruction-level Parallelism
An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor. A brief comparison with Berkeley RISC (reduced-instruction-set-computer) and SOAR is provided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
| Year | Citations | |
|---|---|---|
Page 1
Page 1