IEEE Transactions on Consumer Electronics · 2014 · 16 citations · 15 references
EngineeringComputer EngineeringComputer ScienceComputer GraphicsHardware-software Co-designLow-power DesignData CompressionDigital Image ProcessingDigital Signal ProcessingImage CompressionImage ProcessingSource CodingBit Error RateCodec DecodingComputational Complexity Of AlgorithmsEnergy ConsumptionEnergy-efficient Signal ProcessingLow-power Signal ProcessingPower-efficient DesignVideo Compression
High Efficiency Video Coding (HEVC) intra mode decision algorithm has very high computational complexity. Therefore, in this paper, a computation and energy reduction technique is proposed for reducing the amount of computations performed by Sum of Absolute Transformed Difference (SATD) calculations in HEVC intra mode decision, and therefore reducing the energy consumption of HEVC SATD calculation hardware without any PSNR loss and bit rate increase. The proposed technique reduced the energy consumption of HEVC SATD calculation hardware up to 64.6%. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.
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