A 1–16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator

Abstract

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4-100 MHz) with a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> .