Publication | Closed Access
Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures
95
Citations
10
References
2003
Year
EngineeringComputer ArchitectureGeneric Regular NetworkInterconnection Network ArchitectureRouter DesignScalable RoutingRegular Noc ArchitecturesParallel ComputingEnergy/performance Aware MappingRouting ProtocolRouter ArchitectureComputer EngineeringNetwork On ChipComputer ScienceCommunication SystemNetwork Routing AlgorithmEdge ComputingPower-efficient ComputingTotal Communication EnergyRouting FlexibilityEnergy-efficient Networking
In this paper we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic routing function such that the total communication energy is minimized. At the same time, the performance of the resulting communication system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy/performance aware mapping, in a topological sense, and show how the routing flexibility can be exploited to expand the solution space and improve the solution quality An efficient branch-and-bound algorithm is then described to solve this problem. Experimental results show that the proposed algorithm is very fast, and significant energy savings can be achieved. For instance, for a complex video/audio application, 51.7% energy savings have been observed, on average, compared to an ad-hoc implementation.
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