Scalable high performance main memory system using phase-change memory technology

TLDR

The memory subsystem is a major cost and power consumer, and DRAM-based systems are approaching their limits, prompting investigation of phase‑change memory (PCM) as a denser, cost‑effective alternative that can increase main‑memory capacity while staying within power constraints. The study analyzes a PCM‑based hybrid main‑memory architecture and proposes organizational strategies to reduce PCM write traffic and extend its lifetime. The authors model a hybrid memory comprising PCM storage and a small DRAM buffer, leveraging DRAM’s low latency and PCM’s high capacity, and introduce simple management techniques to curb write traffic. Evaluations on a 16‑core system with 8 GB DRAM show PCM reduces page faults fivefold and yields a three‑fold speedup, while the proposed write‑traffic reductions extend PCM lifetime from 3 to 9.7 years.

Abstract

The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints. In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.