Architecture implementation using the machine description language LISA

TLDR

Application‑specific instruction set processor development involves architecture exploration, software tool design, system verification, and implementation, and the LISA processor design platform (LPDP) offers a unified environment that generates all required software tools from a single specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The authors derive the architectural structure, decoder, and datapath implementation approaches directly from the LISA model. They present the derivation of these components and compare synthesis results of a generated versus handwritten low‑power DVB‑T post‑processing unit.

Abstract

The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design implementation. The LISA processor design platform (LPDP) based on machine descriptions in the LISA language provides one common environment for these design phases. Required software tools for architecture exploration and application development can be generated from one sole specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The derivation of the architectural structure, decoder and even approaches for the implementation of the data path are presented. Moreover the synthesis results of a generated and a handwritten implementation of a low-power DVB-T post processing unit are compared.