Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 · 2015 · 54 citations · 0 references
EngineeringComputer EngineeringComputer ScienceCluster ComputingComputer VisionLow-power DesignAccelerator ArchitectureDeep LearningHardware AccelerationMulticore Processor DesignPower ManagementPower OptimizationConvolutional Neural NetworksEnergy ConsumptionMany-core ArchitectureMany-core ProcessorsMulticore ArchitecturesMulticore SystemsShared MemoryShared-memory Architecture
State-of-art brain-inspired computer vision algorithms such as Convolutional Neural Networks (CNNs) are reaching accuracy and performance rivaling that of humans; however, the gap in terms of energy consumption is still many degrees of magnitude wide. Many-core architectures using shared-memory clusters of power-optimized RISC processors have been proposed as a possible solution to help close this gap. In this work, we propose to augment these clusters with Hardware Convolution Engines (HWCEs): ultra-low energy coprocessors for accelerating convolutions, the main building block of many brain-inspired computer vision algorithms. Our synthesis results in ST 28nm FD-SOI technology show that the HWCE is capable of performing a convolution in the lowest-energy state spending as little as 35 pJ/pixel on average, with an optimum case of 6.5 pJ/pixel. Furthermore, we show that augmenting a cluster with a HWCE can lead to an average boost of 40x or more in energy efficiency in convolutional workloads.