Publication | Closed Access
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
53
Citations
22
References
2014
Year
Unknown Venue
Cluster ComputingEngineeringComputer Architecture36-Core Research ChipInterconnection Network ArchitectureSupercomputer ArchitectureHardware SecurityScalable CoherenceShared MemoryHigh-performance ArchitectureParallel ComputingManycore ProcessorSnoopy CoherenceComputer EngineeringNetwork On ChipComputer ScienceDirectory-based CoherenceCryptographySystem On ChipCo-processorsMany-core ArchitectureParallel ProgrammingScalable Mesh Noc
In the many-core era, scalable coherence and on-chip interconnects are crucial for shared memory processors. While snoopy coherence is common in small multicore systems, directory-based coherence is the de facto choice for scalability to many cores, as snoopy relies on ordered interconnects which do not scale. However, directory-based coherence does not scale beyond tens of cores due to excessive directory area overhead or inaccurate sharer tracking. Prior techniques supporting ordering on arbitrary unordered networks are impractical for full multicore chip designs.
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