Publication | Closed Access
PHIDEO: a silicon compiler for high speed algorithms
87
Citations
8
References
2002
Year
Unknown Venue
Memory OptimisationEngineeringCompiler TechnologyComputer ArchitectureSystem-level DesignEmbedded SystemsProcessor ArchitectureHardware SystemsHardware ArchitectureSilicon CompilerHigh-performance ArchitectureComputer DesignSystems EngineeringParallel ComputingCompilersCompiler SupportComputer EngineeringNew TechniquesHardware OptimizationComputer ScienceHardware AccelerationProgram AnalysisParallel Programming
PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the datapaths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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