Contact Resistance Reduction of Low Temperature Atomic Layer Deposition ZnO Thin Film Transistor Using Ar Plasma Surface Treatment

Abstract

In this work, the effect of Ar plasma at the S/D contact in a low temperature (200°) fabricated ALD ZnO thin-film transistors (TFTs) for contact resistance reduction is systematically studied. With an optimized Ar plasma process time, the contact resistance is significantly reduced by >50% from 170 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$84 {\sf \Omega }/\mu \text{m}$ </tex-math></inline-formula> . This reduction is attributed to the oxygen vacancies modulating the effective contact barrier height, as elucidated by detailed AFM and XPS analysis. Consequently, the effective field-effect mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\textit {FE}}$ </tex-math></inline-formula> ) of the TFT is increased by 50% to 39.2 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\textit {FE}}$ </tex-math></inline-formula> of the developed TFT is one of the highest reported thus far using ALD process at the lowest temperature. The advances achieved in this work provide valuable insight into the defect’s regulation mechanism of ZnO-metal contact and its effect on the TFTs performance. This approach paves a pathway to further develop ZnO TFTs in applications in high-speed computational circuitries.