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A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge<sub>-on-</sub>Si Using HZO Internal Voltage Amplification

22

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34

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2022

Year

Abstract

There are vital challenges to harness the unique assets of germanium (Ge) because of Ge-on-insulator (GeOI) processing issues. The advances in molecular beam epitaxy (MBE) technology have enabled the defect-free growth of atomic-level Ge stacks over the standard monolithic silicon platform to leverage the properties of the Ge as a channel layer. Here, we present the first ever report on the authoritative integration of ferroelectric (FE) hafnium zirconium oxide (HZO) over the p-Ge/n-Ge <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{-on-}\text{n}$ </tex-math></inline-formula> -Si system. A rudimentary approach for the carrier modulation in the channel was employed using depletion approximation and negative capacitance (NC) to fabricate HZO and thin p-Ge channel-based FET. The TaN/HZO/TaN stacks were optimized and characterized for enhanced ferroelectricity and non-centrosymmetric orthorhombic phase, which is further confirmed with piezoresponse force microscopic (PFM) analysis. The trivial loop hysteresis conditions to validate the NCFET operation was discussed. The devices demonstrated a lower subthreshold swing (SS) of ~23.44 mV/dec and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{OFF}}$ </tex-math></inline-formula> ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> . The threshold voltage shift <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{t} = -0.6$ </tex-math></inline-formula> and −1.1 V with the body bias voltage of 0.25 and 0.5 V, respectively. Minimum DIBL measured ~26 mV/V, and rule-out gate induces drain lowering (GIDL) effect due to no gate–drain region overlap.

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