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A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density
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2022
Year
Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer ArchitectureCost Effectiveness Qlc3D MemoryMemory DeviceMemory DevicesCache Read OperationsElectrical EngineeringFlash MemoryComputer EngineeringComputer ScienceMicroelectronicsMemory ArchitectureRandom Read PerformanceSemiconductor MemoryImproved Read Latency
Triple-level-cell (TLC) NAND has prevailed the non-volatile memory market, yet the quad-level-cell (QLC) NAND is emerging as a suitable replacement for low-cost and high-density storage. However, despite its cost effectiveness QLC's market share is not increasing quickly, not only due to its worse reliability but also its slow sequential and random read performance. To increase random read performance an independent plane read operation has been introduced [1], [2], but the read and pass voltage noise, caused by high I/O and data-path current consumption, causes a shift in the threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{th}})$</tex> distribution during plane-interleaved and cache read operations. Furthermore, for QLC with reduced program and erase (P/E) cycles the number raw bit errors exceeds the amount correctable by ECC. More read-retry steps need to be added to compensate, but the read latency increases.