Dynamic thermal management in 3D multicore architectures

TLDR

Technology scaling has shrunk transistor sizes while interconnects have not, prompting 3D stack architectures to reduce interconnect length and power, but these stacks create high power density and severe thermal challenges. This study examines how current thermal, power, and job‑scheduling policies influence the thermal behavior of 3D chips. We introduce a dynamic, thermally‑aware job‑scheduling method that can be coupled with power‑management policies to lower energy use while mitigating hot spots and temperature swings at minimal performance cost.

Abstract

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.