Publication | Closed Access
A 4.6-<i>μ</i>m, 127-dB Dynamic Range, Ultra-Low Power Stacked Digital Pixel Sensor With Overlapped Triple Quantization
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Citations
26
References
2022
Year
Event CameraEngineeringIntegrated CircuitsImage SensorComputational ImagingInstrumentationAnalog-to-digital ConverterDynamic RangeElectrical EngineeringGlobal ShutterComputer EngineeringOverlapped Triple Quantization127-Db Dynamic RangeDigital ImagingMicroelectronicsQuantization (Signal Processing)Image ProcessorDigital Pixel SensorOptoelectronicsCamera Technology
This article presents a global shutter (GS), stacked digital pixel sensor (DPS) to meet the ultra-low power, ultra high dynamic range (HDR) requirements for battery-powered, always-on mobile computer vision (CV) applications. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.6~\mu \text{m}$ </tex-math></inline-formula> DPS pixel is partitioned into two layers; a dual conversion gain (CG) pixel with a backside-illuminated photodiode (PD) on the top layer and an in-pixel ADC circuit with 10 bit SRAM on the bottom layer. A Cu-to-Cu hybrid-bonding (HB) technology is used to connect the two layers via pixel-level interconnect. The sensor features an overlapped triple quantization (3Q) scheme that performs a time-to-saturation (TTS) quantization and the dual-CG linear ADC mode sequentially in the same frame and extends the dynamic range (DR) with a small number of ADC bits. The DPS with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$512\times512$ </tex-math></inline-formula> pixel array has achieved an ultra-HDR of 127 dB and low power consumption of 5.75 mW at 30 frames per second. The nonlinear conversion characteristics of the TTS mode provide an equivalent full well capacity (FWC) of 9000 ke <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> , while the high CG linear ADC mode realizes a low noise floor of 4.2 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> .
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