CMOS-SRAM soft-error simulation system

Abstract

A soft-error simulation system for designing CMOS-SRAM cells is presented. We propose a new noise current model and combine it with the SRAM's equivalent circuit. Simulation results agree with those from a compulsory exposure experiment. Our system predicts the field soft-error rate from the alpha-particle emission rate, mask layout, and process conditions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>