A GaN Complementary FET Inverter With Excellent Noise Margins Monolithically Integrated With Power Gate-Injection HEMTs

Abstract

A GaN complementary field-effect transistor (FET) inverter monolithically integrated with power gate-injection high-electron-mobility transistors (HEMTs) was realized on a Si substrate. The GaN p-channel and n-channel logic devices and power devices were fabricated based on a p-GaN/AlGaN/GaN epi-structure. Through optimization of epi-layer thickness and doping, excellent low-level noise margin (NM_L) of 1.47 V and high-level noise margin (NM_H) of 0.98 V were achieved at a supply voltage <inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula> of 3 V at room temperature. A maximum current density (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {D,max}}$ </tex-math></inline-formula>) of 0.36 mA/mm/220 mA/mm at <inline-formula> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> of &#x2212;3 V/3 V and a threshold voltage <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of &#x2212;2.0 V/&#x002B;2.3 V were achieved in the p-channel and n-channel FETs, respectively. A propagation delay of an inverter stage <inline-formula> <tex-math notation="LaTeX">$\tau _{\text {pd}}$ </tex-math></inline-formula> in a ring oscillator was measured to be <inline-formula> <tex-math notation="LaTeX">$1.67~\mu \text{s}$ </tex-math></inline-formula>. The power gate-injection HEMT has an ON-resistance <inline-formula> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> of <inline-formula> <tex-math notation="LaTeX">$18.7~\Omega \cdot $ </tex-math></inline-formula>mm and a breakdown voltage (BV) of 900 V. These results show the great potential of the developed GaN complementary FET technology in the applications of GaN power modules.