Compact model of retention characteristics of ferroelectric FinFET synapse with MFIS gate stack

Abstract

Abstract In this paper, multiple-fin n- and p-channel HfZrO 2 ferroelectric-FinFET devices are manufactured using a gate first process with post metalization annealing. The device transfer characteristics upon program and erase operations are measured and modeled. The drift in the transfer characteristics due to depolarization field and charge injection are captured using the shift in the threshold voltage along with time-dependent modeling of vertical field dependent mobility degradation parameters to develop a physical, computationally efficient, and accurate retention model for ferroelectric-FinFET devices. The modeled conductance is incorporated into deep neural network simulation platform CIMulator to analyze the role of conductance drift due to retention degradation, as well as the importance of the gap between high and low conductance states in improving the image recognition accuracy of neural networks.