A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics

Abstract

In this paper, a quadrature error corrector (QEC) for next generation DRAM interface is proposed. The proposed QEC corrects duty-cycle error and 4-phase skew simultaneously for high speed operation in DRAMs. The internally used half rate two-phase clocking reduces power by 35% and area by 40%, respectively. A prototype chip achieves less than 1.84° phase error for a 12.8 Gb/s and has a correctable range 100.5° within 120 ns lock-time using successive approximation register (SAR). A relock scheme to cope with voltage and temperature variation during chip operation is also proposed. It occupies an active area of 0.01 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while consuming 9.8 mW with 1.0-V supply.