Interface Engineering for 3-Bit per Cell Multilevel Resistive Switching in AlN Based Memristor

Abstract

Gradual conduction tuning with a large memory window is essential for realizing multilevel switching memristive devices. In this work, we demonstrated 3-bit per cell storage capability with excellent endurance and retention behavior of AlN/AlO memristor via interface engineering. By incorporating an ultra-thin 2 nm Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interface layer, seven distinct high resistance states with same low resistance state were achieved by controlling reset-stop voltage. In addition, by varying set compliance current, six resistance states with reliability and reproducibility were illustrated. The maximum cycle-to-cycle variability <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma /\mu $ </tex-math></inline-formula> (standard deviation/mean) of any resistance state was 28.7% in reset-stop voltage control methods. The multilevel switching characteristics could be attributed to (a) enhancement of on-off ratio resulted due to insertion of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> barrier layer acts as series resistance (b) the gradual electron detrapping from occupied trap sites resulting in multiple intermediate resistance states during reset.