A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET

Abstract

This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LC</i></b> filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fs</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> with nominal output swing of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.0~V_{\mathrm {ppd}}$ </tex-math></inline-formula> at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LC</i></b> phase-locked loop (PLL). To the best of authors’ knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date.