Aging Mechanisms and Accelerated Lifetime Tests for SiC MOSFETs: An Overview

Abstract

Accelerated lifetime tests (ALTs) play a critical role in long-term reliability studies of SiC MOSFETs, including lifetime estimation, failure analysis, and condition monitoring. This article presents a comprehensive review of state-of-the-art ALTs circuits, operating principles, and induced failure modes for SiC MOSFETs. First, the weak spots and corresponding aging mechanisms in both device chip and package are summarized. Next, based on the system operating conditions, ALT configurations and working principles are discussed. Specifically, SiC MOSFET ALTs under normal operation, third-quadrant conduction, and extreme conditions are comprehensively described and compared. Requirements and future trends on ALTs selection and development are comprehensively discussed corresponding to various reliability research directions. Finally, suitable ALTs, corresponding failure locations, and mechanisms are tabulated as the conclusion. This review intends to provide insight on SiC MOSFET reliability test selection, platform development, and test parameter adjustments depending on application requirements.