SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

Abstract

This brief presents SRAM write assist circuit using cell supply voltage self-collapse with bitline charge sharing (SC-BCS) that can lower the minimum operating voltage to the near-threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> ) region while consuming a minimal write energy. The proposed SC-BCS improves the write-ability by utilizing the cell supply voltage (CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) self-collapse and the feedback operation through the detection of write failure. Because the amount of CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> collapse is regulated automatically depending on the write-ability of the selected cell, the write energy of the proposed SC-BCS is effectively reduced. The proposed SC-BCS can achieve a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 \boldsymbol{\sigma }$ </tex-math></inline-formula> write-ability yield with a smaller delay overhead than gate-modulated self-collapse and self-collapse write assists in the near- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> region. In addition, the proposed SC-BCS consumes the lowest write energy with minimal delay overhead or without any delay overhead compared with the strong-bias transient CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> collapse and pulsed-pMOS transient CV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> collapse. The measurement result of the test chip fabricated using 65-nm CMOS technology indicates that the proposed SC-BCS can operate without any failure up to 0.36 V consuming write power 12.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> /MHz.