Design and Implementation of a Power Efficient BIST

Abstract

According to Moore's law, the number of transistors in a chip doubles every eighteen months. Since, the number of transistors is increasing, the probability of finding a fault in the transistors also increases. In order to detect the faults and to avoid potential faults, testing is necessary. In this paper, a power efficient Built-In-Self-Test (BIST) is designed using bit-swapping LFSR and a modified MISR for testing a combinational circuit. The Bit-swapping LFSR is used as the Test Pattern Generator (TPG) and the modified MISR is used as the Output Response Analyzer (ORA). The TPG produces the test patterns, which is given as inputs to the Circuit Under Test (CUT). The ORA analyzes the outputs of the CUT and a pass/fail signal is generated which indicates whether there are any faults in the circuit. This BIST architecture can detect single stuck-at faults present in a combinational circuit. The results were simulated in Xilinx ISE Design Suite 14.4 using VHDL and synthesized in Vivado 2018.2.