A 32Gb MLC NAND-flash memory with V<inf>th</inf>-endurance-enhancing schemes in 32nm CMOS

Abstract

A 32 nm 32 Gb MLC flash memory, with MSB even page re-program, dramatically improves floating-gate (FG) coupling-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -widening while FG coupling cancellation program verify read minimizes performance loss due to additional program operation allowing throughput of 13.0 MB/S. More than 30% improvement in retention-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -shift and additional 50 mV reduction of cell Vth distribution is achieved by moving-read and adaptive code selection. Die size of the device is 146 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 3M 32 nm CMOS.