2009 · 154 citations · 20 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingFault-tolerant SystemsFault Tolerance DesignHardware Fault ToleranceNetwork-on-chip DesignRoutingRouting AlgorithmsRouting Architecture2-D Torus NetworksFailure Resilient RoutingFault-tolerant Interconnection NetworksFault-tolerant InterconnectsFault-tolerant NetworksFault-tolerant RoutingNetwork-on-chip ArchitecturesResilient Routing
Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will soon make long-term product reliability extremely difficult in complex modern systems such as systems on a chip (SoC) and chip multiprocessor (CMP) designs, where even a single device failure can cause fatal system errors. Resiliency to device failure will be a necessary condition at future technology nodes. In this work, we present a network-on-chip (NoC) routing algorithm to boost the robustness in interconnect networks, by reconfiguring them to avoid faulty components while maintaining connectivity and correct operation. This distributed algorithm can be implemented in hardware with less than 300 gates per network router. Experimental results over a broad range of 2D-mesh and 2D-torus networks demonstrate 99.99% reliability on average when 10% of the interconnect links have failed.
20
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
Shane Bell, Bruce Edwards, John Amann et al. · 2008 · 641 citations
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
Sriram Vangal, Jason Howard, Greg Ruhl et al. · IEEE Journal of Solid-State Circuits · 2008 · 627 citations