A 19.1-dBm Fully-Integrated 24 GHz Power Amplifier Using 0.18-¿m CMOS Technology

Abstract

A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the author's knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 G.Hz in CMOS processes.