A 25 ns 4 Mb CMOS SRAM with dynamic bit line loads

Abstract

A 4-Mb CMOS SRAM (static RAM) with an access time of 25 ns designed for a single 3.3-V supply voltage and a 400-mil DIP (dual-in-line) package, using a 0.5- mu m double-polysilicon and double-aluminum CMOS technology, is presented. A 25-ns address access time was achieved by a dynamic bit-line-load circuit scheme combined with an address transition detector (ATD), divided word line structure, and three-stage sense amplifier approach. The hierarchical structure of the memory cell array with 512-kw*8-b organization is shown. Active operating currents of 33 mA and 46 mA have been obtained at 10 MHz and 40 MHz, respectively. A standby current of 70 mu A has been realized at V/sub cc/=3.3 V and V/sub IH/=2.2 V. The RAM output waveforms for address access with 30-pF load capacitance are shown. The characteristics of the RAM are summarized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>