The next-generation 64b SPARC core in a T4 SoC processor

Abstract

The T4 microprocessor introduces the next generation dual-issue, out-of-order SPARC core that delivers up to 5× integer and 7× floating-point single-thread performance improvement for both commercial and industry standard workloads. Eight SPARC cores, a crossbar and a unified 16-way 4MB L3 cache are implemented in the same system-on-chip platform as the predecessor T3 [1] to utilize established coherency (CLC), DDR3 (MCU), PCIE Gen2 (PEU) and 1G/10G Ethernet interfaces (NIU) (Fig. 3.3.1). Further, T4's pin, thermal and power compatibility with the previous generation enables faster time to market for new multi-socket systems. The 403mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die has 855 million transistors of four different types and 12 metal layers fabricated using TSMC's 40nm process.