2D MoS₂ Charge Injection Memory Transistors Utilizing Hetero‐Stack SiO₂/HfO₂ Dielectrics and Oxide Interface Traps

Abstract

Abstract Among advanced devices with 2D semiconductors, charge injection memory field effect transistors (CIM FETs) may be one of the most important and practical ones. Reported CIM FETs utilize three layers (for tunneling, trapping, and bulk dielectric) in general, resulting in high switching voltages over 10 V. Here, nonvolatile CIM FETs are fabricated with MoS 2 channel and hetero‐stack bilayer oxide dielectrics adopting 5 nm‐thin SiO 2 and 25 nm‐thick HfO 2 , where the charge traps are expected at the SiO 2 /HfO 2 oxide interface. It is nicely observed from the device that a low pulse gate voltage below ±7 V is enough to obtain program and erase states, which would originate from the tunneling electrons trapped at the hetero‐stack oxide interface. For comparison, other CIM FET devices are also fabricated but with tri‐layer dielectric of 5 nm polystyrene‐brush/5 nm HfO 2 /25 nm SiO 2 . Expectedly, the latter with tri‐layer requires at least ±10 V for memory operations. The former with a hetero‐stack oxide bilayer is now determined as an optimum device because of low operating voltages and less process complexity, and it is extended to a circuit application for a long‐term memory switching of an organic light‐emitting diode (OLED) pixel.