Size-Controlled Polarization Retention and Wall Current in Lithium Niobate Single-Crystal Memories

Abstract

Highly conductive domain walls in insulating ferroelectric LiNbO₃ (LNO) single-crystal thin films with atomic smoothness are attractive for use in high-density integration of the ferroelectric domain wall random access memory (DWRAM) because of their excellent reliability and high read currents. However, downscaling of the memory size to the nanoscale could cause poor polarization retention. Understanding the size-dependent electrical performance of a memory cell is therefore crucial. In this work, highly insulating X-cut LNO thin films were bonded to SiO₂/Si wafers and lateral mesa-like cells were fabricated on the film surfaces, where contact occurred with two-sided electrodes along the polar <i>z</i>-axis. Under application of an in-plane electric field above a coercive field (<i>E</i>_c), the domain within each memory cell was switched to be antiparallel to the unswitched referencing domain at the bottom; this resulted in the formation of a conducting domain wall, which enables the nondestructive readout strategy of the DWRAM. The cell, which has a lateral length (<i>l</i>) above a critical size (<i>l</i>₀) of 105 nm, is found to be a mixture of two phases across the cell area. The inner area of the cell suffers from poor polarization retention because <i>E</i>_c = 150 kV/cm, as demonstrated by in-plane piezoresponse force microscopy imaging. In comparison, the outer periphery domains, which have lengths of 70 nm (∼<i>l</i>₀/2), show good retention but require a much higher <i>E</i>_c of 785 kV/cm. The relevant physics is discussed as phase reconstruction occurs after release of the in-plane compressive strain near the outer regions; the results show good agreement with those of one-dimensional thermodynamic calculations and phase-field simulations. The measured current-voltage curves demonstrated a sudden enhancement of the wall current across the cell when <i>l</i> < <i>l</i>₀, thus implying higher readout wall currents and better retention for the DWRAM at higher storage densities.