Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

TLDR

Conventional von Neumann architectures hinder AI edge devices by causing a memory‑wall bottleneck that degrades energy efficiency, while computing‑in‑memory (CIM) and SRAM cells offer a promising, endurant, logic‑compatible alternative. The paper surveys the background, trends, and challenges for advancing SRAM‑based CIM macros. It reviews silicon‑verified SRAM‑CIM macros that perform logic and multiplication‑accumulation operations.

Abstract

When applied to artificial intelligence edge devices, the conventionally von Neumann computing architecture imposes numerous challenges (e.g., improving the energy efficiency), due to the memory-wall bottleneck involving the frequent movement of data between the memory and the processing elements (PE). Computing-in-memory (CIM) is a promising candidate approach to breaking through this so-called memory wall bottleneck. SRAM cells provide unlimited endurance and compatibility with state-of-the-art logic processes. This paper outlines the background, trends, and challenges involved in the further development of SRAM-CIM macros. This paper also reviews recent silicon-verified SRAM-CIM macros designed for logic and multiplication-accumulation (MAC) operations.