8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS

Abstract

Wireline IOs have doubled per-lane data-rate every 3-4 years over the last two decades due to increasing demand in high-performance computing, networking/communications, and most recently from machine learning and AI. To address the need for higher throughput, this paper presents a 224Gb/s DAC-based PAM-4 TX with 8-tap FFE in 10nm CMOS technology. Doubling the data-rate from 112Gb/s while supporting the same PAM-4 modulation requires doubling the pad and internal net bandwidth and reducing the clocking jitter and circuit noise PSD by $2 \times $ while maintaining swing, linearity, and reliability requirements. These are addressed by combining a low-noise on-chip LC-PLL, an inductive clock distribution network with jitter filtering, a two-stage 4:1 MUX with active peaking, and a group-delay-optimized output matching network for signal integrity.