Investigation on Single Pulse Avalanche Failure of 1200-V SiC MOSFETs via Optimized Thermoelectric Simulation

Abstract

The dynamic avalanche reliability of 1200-V silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) is studied in this article. The unclamped inductive switching (UIS) tests are conducted to locate failure points. An optimized thermal network model with the definition of the material above the epitaxial layer is used to simulate the avalanche process of SiC MOSFETs. The simulation and experiment results are matched, which verifies the validity of this model. Further simulation results show that a slight change in the doping profile of the p-well region will make the avalanche capability significantly different. Then, the effect of the deviation in cell parameters on the avalanche capability is studied by multicell simulation. The results demonstrate that uneven distribution of internal parameters makes the parasitic bipolar junction transistor (BJT) of some cells turn-on first, causing a significant concentration of current and heat in a very short time, and eventually forming hot spots often observed in failed devices.