Cryogenic Characteristics of Multinanoscales Field-Effect Transistors

Abstract

The cryogenic performance of multinanoscale CMOS transistors with a standard 55-nm Si-bulk technology is systematically investigated by dc measurements. In contrast to 300 K, the cryogenic drain saturation current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {dsat}}$ </tex-math></inline-formula> ) gain significantly enhances from 54% to 167% with the increasing channel length and has a relatively weak response to width change. In addition, the degraded subthreshold swing (SS) due to the short channel effect is alleviated at lower temperatures. The merits of a typical nMOS transistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W}/{L} = 0.6~\mu \text{m}$ </tex-math></inline-formula> /60 nm) worked at 4.2 K are associated with an improved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {dsat}}$ </tex-math></inline-formula> (~1.3 times), decreased drain leakage current with three orders of magnitude, and 2/3 reduced SS. However, the cryogenic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {dsat}}$ </tex-math></inline-formula> tends to saturate below 10 K and the threshold voltage increases, as well as barrier lowering induced by drain voltage, starts to deteriorate. The detailed analyses on these MOSFET (deep) cryogenic characteristics are implemented based on the comprehensive semiconductor physics images, including energy band change, temperature/geometry-dependent scattering, band-to-band tunneling process, and depletion width influence. Our findings will be beneficial for the community to design ultralow temperature-integrated circuits.