IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 16 citations · 34 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSystem-on-chip DesignWireless CommunicationsDigital Signal ProcessingWireless NetworksCholesky DecompositionDecouplingHardware ResourcesLattice ReductionMimo SystemsMultiple Input Multiple Output CommunicationsMultiple-input Multiple-output CommunicationThroughput
This article presents an 8 × 8 lattice-reduction-aided (LRA) soft-output multiple-input multiple-output (MIMO) detector for Chinese enhanced ultrahigh throughput (EUHT) wireless local area network (LAN) standard. The preprocessing algorithm combining simplified-sorting Cholesky decomposition and low-complexity decoupled lattice reduction (LDLR) is proposed to reduce computational complexity and latency with parallelism improvement. In addition, K-best detection adopts a sorting-reduced strategy utilizing approximate ordered sequence. Compared with other published LRA K-best detection algorithms, simulation results show that our proposed algorithm has performance improvement. In addition, in order to save hardware resources, a folded K-best architecture and an optimized intermediate storage strategy are introduced. Furthermore, a fully pipelined VLSI architecture is designed in Semiconductor Manufacturing International Corporation (SMIC) 40-nm 1P9M technology to support the 8 × 8.64 -QAM MIMO-OFDM system. The detector can achieve 3.85-Gb/s data throughput at 641-MHz clock frequency with 0.71-μs latency. The proposed detector is competitive in terms of latency, throughput, and area efficiency to state-of-the-art works and can meet the data-rate requirement of the EUHT standard.
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Factoring polynomials with rational coefficients
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