Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications

Abstract

Adders play a crucial role and are one of the fundamental building blocks in application like signal processing. In the modern scenario, integrated circuits are majorly used in which the requirement of adder module is vital. This paper addresses various forms of adders which include Ripple-carry (RC), Carry-skip (CSk), Carry-lookahead (CL) and Kogge-stone(KS) adders. These adders can meet certain design constraints in digital VLSI circuits, such as speed and area. For various bit-lengths, a new KS adder is proposed in this paper which was analyzed on the basis of delay. The proposed adder with 8, 16, 32, 64 and 128 bit-length results in 7.487ns, 9.248ns, 10.295ns, 7.259ns and 6.814ns delay respectively. 84.11% improvement has been analyzed for 128 bit KS adder in comparison with CSk adder, 88.34 % in comparison with RC adder and 88.83% in comparison with CL adder. The proposed KS architecture can be used in time critical FPGA based signal processing applications.