Impact of Graded Back-Barrier on Linearity of Recessed Gate InAlN/GaN HEMT

Abstract

Work presented in this paper reports the impact of graded AlGaN back-barrier on the linearity performance of lattice-matched InAlN/AlN/GaN recess gate device. Specifically, a comparison is made on the linearity of the proposed device with and without a graded back barrier layer. Various device performance matrices namely transconductance (gm) and its higher-order derivatives, second and third-order voltage intercept point (VIP2, VIP3), 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order input intercept point (IIP3), 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> inter-modulation distortion (IMD3) and 1-dB compression point have been investigated and discussed for the proposed device architecture. Results obtained from TCAD simulation of the proposed device confirms that by using graded back-barrier the linearity performance matrices of the device are improved, which further shows that the proposed device is also suitable for wireless applications.