A 29.2 Mb/mm² Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit

Abstract

A 29.2Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ultra high density SRAM macro has been proposed using 7-nm CMOS FinFET technology. The SRAM macro has only one SRAM cell array despite of the huge array of 512 rows × 512 columns. The circuitry of dual-edge driver for such long wordline and bitline in such huge array are newly proposed. The SRAM macro using proposed circuit was designed, and a test chip was fabricated using 7-nm CMOS FinFET technology. The minimum operation voltage is improved 170 mV by the new circuits.