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Chip Package Interaction (CPI) risk assessment of 22FDX<sup>®</sup> Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling
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2020
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EngineeringWlcsp ModelMechanical EngineeringChip Package InteractionComputer-aided DesignAdvanced Packaging (Semiconductors)Modeling And SimulationElectronic PackagingElectrical EngineeringHardware ReliabilityChip On BoardComputer EngineeringChip AttachmentCpi Failure RiskMicroelectronicsRisk AssessmentAdvanced PackagingChip-scale PackageChip-package InteractionMechanics Of Materials
In order to address the Chip-Package Interaction (CPI) risks associated with the Wafer Level Chip Scale Package (WLCSP), GLOBALFOUNDRIES has developed Finite Element (FE) models to simulate the mechanical stress in the Backend of Line (BEoL) and Far Back End of Line (FBEoL) during mass reflow process. This paper discusses the CPI failure risk associated with WLCSP, modeled with and without the redistribution layers (RDL) introduction above the BEoL. The WLCSP model has been modified to assess the design variations within the RDL and the FBEoL. The paper also highlights the FE model verification between the two-dimensional (2D) versus the three-dimensional (3D) models and validation by comparing the simulation results to the experimental test data.