IEEE Transactions on Circuits & Systems II Express Briefs · 2020 · 19 citations · 10 references
EngineeringCommunicationElectrical EngineeringAnalog ElectronicsDigital CommunicationLow-power DesignCmos Circuit DesignDigital Integrated Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignDelay ControlFeedback DelayFin Field-effect TransistorsPower ConsumptionPower EfficiencySignalsSiliconTransceiver Design
The implementation of an unclocked DFE (UC-DFE) architecture for high-speed PAM-4 signals is investigated in this brief. Instead of clocked slicers and flip-flops, data-decision and feedback delay control are performed by saturated analog delay chains. As a result, the UC-DFE, previously exploited for NRZ signals, saves power consumption and silicon area while the simple implementation allows operation at high data-rate. A receiver front-end comprising a linear equalizer and the proposed 2-tap UC-DFE scheme is designed in 7 nm FinFET technology. From post-layout simulations, the receiver recovers a PAM-4 signal at 112 Gb/s after an 18 dB loss channel with a power efficiency of 0.47 pJ/bit. The receiver also works with NRZ signals at half the bit-rate equalizing 24 dB channel loss with a power efficiency of 0.70 pJ/bit.
10
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS
Pen-Jui Peng, Jeng-Feng Li, Li‐Yang Chen et al. · 2017 · 107 citations
Engineering, Computer Engineering, Electrical Engineering +12