Computationally efficient compact model for ferroelectric field-effect transistors to simulate the online training of neural networks

Abstract

Abstract In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field-effect transistors (FETs) with Hf 0.5 Zr 0.5 O 2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.