17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth

Abstract

In this work, a low-power and low-resolution continuous-time charge-integrating DAC (QDAC), which offers a superior noise performance compared to a conventional voltage DAC (VDAC), has been implemented to generate the FMCW chirps. The QDAC generates a smooth output-frequency change, which attenuates the signal replicas due to a stepped change in frequency during the VDAC operation. TPM with the QDAC in the highpass data-injection path is used to generate a 51.2μs saw-tooth chirp with a 1.21 GHz bandwidth at 10GHz, while the PLL consumes less than 12mW of power. To enhance the chirp linearity, a robust background calibration algorithm is implemented to calibrate the nonlinearity of the highpass modulation path. It can be enabled at the chip power-on with less than 700μs of convergence time. After calibration, the rms frequency error is below 90kHz.