High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector - Concepedia

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High data-rate readout logic design of a 512 × 1024 pixel array dedicated for CEPC vertex detector

12

Citations

5

References

2019

Year

Xiaomin Wei, Wei Wei, Tianya Wu, Ying Zhang, X. Li, L. Zhang, Weiguo Lu, Z. Liang, J. Dong, Lanlan Li,

Journal of Instrumentation

Abstract

International audience

References

	Year	Citations

Page 1